The present invention relates to a semiconductor device and to technology for the manufacture thereof; and, more particularly, the invention relates to a semiconductor device having a protection circuit with a thyristor structure and to a technology applicable to a process for manufacturing the semiconductor device.
With advances in micro-fabrication technology in the manufacture of semiconductor devices, the scale-down of elements, wirings, etc., which constitute a semiconductor device, has been an essential element. Correspondingly, the performance of the semiconductor device has increasingly been improved. On the other hand, however, a problem arises in that the scaled-down elements, wirings, etc. are so sensitive to an overvoltage, such as produced by static electricity or the like, that they are apt to break down. There has been a strong demand for the development of mechanisms to prevent degradation and destruction of semiconductor devices due to static electricity or the like and the establishment of a protection structure.
Meanwhile, the present inventors have investigated a protection circuit having a thyristor structure. As a result of this investigation, it has bee found that, for example, Japanese Patent Application Laid-Open No. Hei 8(1996)-306872 discloses a structure wherein a gate terminal and a source terminal of a protection MOS field effect transistor, which is connected to an input terminal, are electrically connected to a ground potential through a trigger terminal of a parasitic PNPN thyristor and an equivalent substrate resistor connected between the collector and emitter of an NPN transistor in the parasitic PNPN thyristor. This technology concerns a circuit structure wherein the potential applied to the base of the NPN transistor is increased based on a voltage drop developed across the equivalent substrate resistor between the collector and emitter to thereby drive the parasitic PNPN thyristor. The cited publication also discloses a technology wherein a parasitic PNPN thyristor and a protection MOS field effect transistor are provided on a semiconductor layer placed on an insulating substrate.
However, the present inventors have found that a protection circuit having a thyristor structure has the following problems.
First of all, a problem arises in that the turn-on time for the thyristor constituting the protection circuit is delayed. In the technology according to the above-described publication, for example, when a surge voltage is applied to the input terminal, the voltage drop developed across the equivalent substrate resistor exceeds the base-to-emitter voltage of the NPN transistor owing to a current which began to flow due to drain-source breakdown of the protective MOS field effect transistor, whereby the parasitic PNPN thyristor is driven for the first time. Therefore, the turn-on time of the thyristor is delayed.
Secondly, a problem arises in that the device design of a protection circuit having a thyristor structure is difficult. Since the equivalent substrate resistor is affected by a sensitivity characteristic of the parasitic PNPN thyristor in the technology according to the above-cited publication, for example, it is necessary to set its sensitivity characteristic to a suitable value. Since, however, the equivalent substrate resistor varies in its vertical structure (e.g., size, impurity distribution) for each process, it is difficult to form the equivalent substrate resistor in such a manner that the sensitivity characteristic is brought to a suitable value.
Thirdly, a problem arises in that it is difficult to cope with miniaturization or scale-down of each element in an internal circuit. Since the breakdown voltage of the protective circuit is used to protect each element in the internal circuit, it is necessary for the breakdown voltage thereof to be lower than the gate withstand voltage of the internal circuit. However, in the above-cited publication technology, for example, a drain-source breakdown current of the protective MOS field effect transistor begins to flow only when the voltage applied to the input terminal exceeds the sum of a drain-source breakdown voltage of the protective MOS field effect transistor and a base-emitter voltage of a parasitic bipolar transistor. Therefore, it is difficult to set the breakdown voltage of the protection circuit lower than the withstand voltage of a gate insulator for each element in the internal circuit according to the scale-down of each element in the internal circuit.
Fourthly, a problem arises in that, when a so-called SOI (Silicon On Insulator) substrate is used, wherein an element forming a semiconductor layer is provided on an insulating layer, it is difficult for a current produced due to static electricity or the like to escape, whereby the protection circuit needs to have a high discharge capability. Since complete element separation is allowed when the SOI substrate is used, the wiring-to-substrate parasitic capacitance, the diffusion or diffused capacitance, etc. can be reduced, and the operating speed of a semiconductor device can be increased. Accordingly, this substrate is suitable for a semiconductor device having a high-frequency signal circuit. However, while complete element separation is allowed, it is hard for an overcurrent produced clue to static electricity or the like to escape, and element breakdown also will easily take place. Therefore, the protective circuit needs to have high discharge capability (sensitivity) when used in a semiconductor device having a SOI substrate.
An object of the present invention is to provide a technology capable of shortening the turn-on time of a thyristor which constitutes a protection circuit.
Another object of the present invention is to provide a technology capable of facilitating the device design of a protection circuit having a thyristor structure.
A further object of the present invention is to provide a technology capable of implementing a protection circuit configuration which copes with the scale-down of each element in an internal circuit.
A still further object of the present invention is to provide a technology capable of improving the discharge capability of a protection circuit having a thyristor structure.
The above, other objects and novel features of the present invention will become apparent from the description provided herein and from the accompanying drawings.
Summaries of typical aspects of the invention disclosed in the present application will be set forth in brief as follows.
The present invention is featured in that a semiconductor layer is provided on an insulating layer; a thyristor for protection and a trigger element for inducing the driving of the thyristor are provided within the same semiconductor layer separated by a separator extending from the main surface side of the semiconductor layer to the insulating layer; and the gate of the thyristor for protection and a substrate electrode portion of the trigger element are provided within the same semiconductor region and are electrically connected to each other to thereby drive the thyristor, based on a substrate current produced by the breakdown of the trigger element.
Also, in accordance with the present invention, a diode for protection, which is electrically connected between a signal terminal and a terminal for a reference potential in such a manner that the direction of the connection therebetween is taken in the forward direction when an overvoltage is applied to the signal terminal, is provided within the same semiconductor layer.
Further, in accordance with the present invention, a high melting-point silicide layer is provided on a surface layer of a semiconductor region for forming the thyristor for protection and the trigger element.
Furthermore, in accordance with the present invention, a resistor is electrically connected between the substrate electrode portion of the trigger element and the terminal for the reference potential.
Still further, in accordance with the present invention, a resistor is electrically connected between the base of a first bipolar transistor of the thyristor for protection and the signal terminal.
Still further, in accordance with the present invention, the trigger element and each element in an internal circuit are formed upon the same process step.
Still further, in accordance with the present invention, the trigger element is formed in association with each element in the internal circuit.